1. Field
The following description relates to a direct current (DC)-DC converter. The following description also relates to a ramp circuit that improves output characteristics by appropriately compensating a slope of a ramp signal according to an input voltage and an output voltage of a current-controlled mode DC-DC converter, and a corresponding DC-DC converter.
2. Description of Related Art
DC-DC converters include an inductor and a power switch, and are configured to store input power in the inductor and transmit the power. It is theoretically possible for a DC-DC converters have 100% efficiency, or close to such efficiency. Therefore, as recent integrated circuit technology has developed, two or more DC-DC converters are used as an efficient power management circuit in the field of portable apparatus design. Such DC-DC converters are also used in fields of design for apparatuses that require considerable power, such as displays for computers, home appliances, or lights for vehicles.
DC-DC converters are divided into two types of DC-DC converters, including DC-DC converters that use a voltage-controlled mode and DC-DC converters that use a current-controlled mode, according to the control method that is used in the DC-DC converter.
A voltage-controlled mode DC-DC converter includes a simple design because the voltage-controlled mode DC-DC converter generates a pulse for driving a power switch only using a specific output voltage. However, because the DC-DC converter operates in a switching frequency lower than an LC resonant frequency in order to have stable frequency stability, the voltage-controlled mode DC-DC converter has a small frequency range.
Alternatively, because a current-controlled mode DC-DC converter generates a pulse for driving a power switch using an inductor current, the current-controlled mode DC-DC converter operates more stably than in the voltage-controlled mode, without a limitation of an LC resonant frequency. The current-controlled mode DC-DC converter must sense the inductor current stably without reduction of an efficiency. However, the current-controlled mode DC-DC converter reduces the number of devices outside the chip or a size of the device by comparison to a DC-DC converter in the voltage-controlled mode. Therefore, the current-controlled mode DC-DC converter is used in various fields for purposes where these aspects are beneficial.
The current-controlled mode DC-DC converter uses a ramp signal as a signal for generating a pulse width modulation (PWM) signal. The PWM signal produced from the ramp signal is used to remove sub-harmonic oscillation produced by the DC-DC converter. Thus, in the current-controlled mode DC-DC converter, when an output power is larger than an input power, a PWM signal has a duty ratio of 50% or more, and an inductor current operates in a continuous current mode (CCM). When the current-control mode DC-DC converter operates in a CCM mode, and requires a duty ratio 50% or more, there is sub-harmonic oscillation. For example, there is sub-harmonic oscillation in which the inductor current is oscillated in a 1/N frequency of a base wave is caused due to characteristics of an inductor. When the duty ratio is 50% or less, the sub-harmonic oscillation is not caused, and hence the ramp signal is not used.
The ramp signal used for preventing the sub-harmonic oscillation of the current-controlled mode DC-DC converter has a sawtooth shape having a certain slope. The ramp signal is closely related to a sensing signal used for sensing a current flowing in an inductor or a power switch. That is, the ramp signal has to be output so as to remove the sub-harmonic oscillation, after slope compensation is performed, to provide a suitable slope to be used as the sensing signal. The slope compensation of the ramp signal is described with reference to FIG. 1.
FIG. 1 is a waveform diagram illustrating a relationship between a sensing signal and a slope of a ramp signal in a current-controlled mode DC-DC converter. Hereinafter, a current-controlled mode DC-DC converter is referred to simply as a DC-DC converter, although certain aspects of certain examples may also apply to a voltage-controlled mode DC-DC converter.
In FIG. 1, (a) is a waveform of a sensing signal (SENSE), (b) is a waveform of a ramp signal (RAMP), and (c) is a waveform of a signal (VISEN) in which the sensing signal and the ramp signal are combined. The signals are signals that are applied to a non-inverting (+) terminal of a comparator configured to generate a PWM signal for the DC-DC converter. In FIG. 1, the reference numeral m1 denotes a rising slope of the sensing signal, m2 denotes a falling slope of the sensing signal, and m3 denotes a slope value of the ramp signal.
The suitable slope compensation in the DC-DC converter of FIG. 1 has to satisfy a condition in which the slope m3 of the ramp signal is at least twice as large as the falling slope m2 of the sensing signal.
That is, Equation 1 is as follows, and summarizes a condition for the relationships between the slopes.m3≧(m2−m1)×0.5  Equation 1
Here, m1≧Vin/L, m2≧(Vout−Vin)/L. Vin is the input voltage, and Vout is the output voltage.
The slope m3 and falling slope m2 have opposite signs, because slope m3 must have a value that compensates for falling slope m2.
A magnitude of the rising slope m1 of the sensing signal is proportional to an input voltage of the DC-DC converter. Additionally, a magnitude of the falling slope m2 of the sensing signal is proportional to a difference between an output voltage and the input voltage of the DC-DC converter. Therefore, when the input voltage is increased, the falling slope m2 decreases, and when the output voltage is increased, the falling slope m2 increases.
Theoretically, when a value of the slope m3 of the ramp signal is set to 0.5 times of m2, slope compensation is successful for all duty ratios.
However, due to relationships between the rising slope and the falling slope and between the input voltage and the output voltage, the value of the slope m3 of the ramp signal has to be set based on both the output voltage and the input voltage. When the value of the slope m3 of the ramp signal is not suitably compensated, several issues arise. When the slope m3 of the ramp signal is too small, the sub-harmonic oscillation is not removed properly. When the slope m3 of the ramp signal is too large, input/output characteristics of the DC-DC converter are degraded. For example, a dynamic characteristic of the DC-DC converter is degraded or usable power is reduced.
To maintain a stable operation state of the DC-DC converter, the slope m3 of the ramp signal is restricted to have a suitable value. Thus, as described above, compensation is continuously made to maintain the slope as being at least twice larger than (m2−m1), as presented in Equation 1, above. To this end, a ramp circuit for slope compensation is used. Such a ramp circuit compensates slope m3 to cause it to maintain a suitable value.
FIG. 2 is a view illustrating a configuration of a ramp circuit.
The ramp circuit 10 includes an operation amplifier 12. The operation amplifier 12 receives a first voltage (VA) that is affected by an output voltage, applied to a non-inverting (+) terminal of the operation amplifier 12.
The ramp circuit 10 also includes a first PMOS transistor 14 to which a power voltage (VDD) is applied to its source, and a first NMOS transistor 16 of which a drain is connected to a drain of the first PMOS transistor 14. An output signal of the operational amplifier 12 is input to a gate of the first NMOS transistor 16, and a source signal of the first NMOS transistor 16 is applied to an inverting (−) terminal of the operational amplifier 12.
A resistor (R) of which one side is connected to a ground is also connected to a source of the first NMOS transistor 16.
A second voltage (NA) of the operational amplifier 12 is applied to a node a between the first NMOS transistor 16 and the resistor (R).
The ramp circuit 10 also includes a second PMOS transistor 18 that forms a current mirror structure with the first PMOS transistor 14. The second PMOS transistor 18 receives the power voltage (VDD) at a source. A capacitor (C) of which one side is grounded is connected to a drain of the second PMOS transistor 18. An output terminal, which outputs a ramp signal (RAMP), is connected to a node b between the second PMOS transistor 18 at a drain and the capacitor (C). A switch (SW), configured to turn on and off according to a reset signal (RESET), is connected parallel to the capacitor (C).
The ramp circuit 10 for slope compensation copies a current flowing through the resistor (R), that is, a current value VA/R in which an interlock voltage (VA) is divided by the resistor (R) using a current mirror structure to the second PMOS transistor 18. The ramp circuit 10 charges/discharges a current flowing through the drain of the second PMOS transistor 18 into the capacitor (C). Accordingly, the ramp signal (RAMP) generated according to the charge/discharge operation is output through an output terminal connected to the node b.
However, the ramp circuit in this approach generates the ramp signal by considering only output voltage, as described above.
When a slope of the ramp signal is set by considering a case in which an input voltage is at its lowest, excessive slope compensation is potentially performed when the input voltage is increased. Thus, the excessive slope compensation potentially leads to slope compensation that is more than a preset driving range, to impair dynamic characteristics of the DC-DC converter.
When the input voltage is reduced with respect to the driving range that the ramp circuit is able to compensate for, the slope compensation is not accomplished, and thus the sub-harmonic oscillation is still present. This means that the ramp circuit, which is used for eliminating the sub-harmonic oscillation, is not functioning properly.
As described above, since the slope-compensated ramp signal is generated in the previous examples based only on the output voltage of the DC-DC converter, the scenario in which an oscillation or degradation of input/output characteristics of the DC-DC converter is generated by a change in the input voltage, is not completely eliminated.